Example embodiments relate to semiconductor logic circuits, and more particularly, to a clock-delayed domino logic circuit having a noise compensation scheme.
As a demand for a high-performance mobile central processing unit (CPU) gradually increases, a digital circuit capable of high-speed operating within the CPU becomes more important. A domino logic is currently used as the digital circuit. The domino logic is a CMOS-based evolution of dynamic logic techniques that are based on PMOS transistors or NMOS transistors.
The domino logic includes cascade-connected stages, and a delay circuit for delaying a clock signal is included between the cascade-connected stages. The domino logic having such a structure is referred to as a clock-delayed domino logic. A signal of a dynamic node of each of the stages is vulnerable to coupling noise.